Fast flip-flop structure with reduced set-up time

ABSTRACT

A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of U.S. Provisional PatentApplication Ser. No. 61/169,467, filed on Apr. 15, 2009, which isincorporated herein by reference in its entirety.

TECHNICAL FIELD

This disclosure relates generally to a flip-flop structure with improvedset-up time.

BACKGROUND

FIG. 1A is an example circuit block diagram of a typical delay path in adigital circuit. The delay path is widely applied to microprocessors andother digital circuits. The flip-flop 102 is coupled to a flip-flop 106through combination logic 104. In the flip-flops 102, 106, D is the datainput end, Q is the data output end, and CK is the clock signalreceiving end. The flip-flops 102, 106 are controlled by the clocksignal. FIG. 1B is an example clock diagram of the operating delay ofFIG. 1A. Referring to FIG. 1A and FIG. 1B, during the first positivetriggering of the clock signal, the flip-flop 102 releases data to thecombinational logic unit 104. At this time, before the data is exactlydisplayed by the flip-flop 102, a CK-Q (clock versus output value) delaytime interval 114 occurs. Once the data is generated by the flip-flop102, it is input into the flip-flop 106 though the combinational logic104, and the time interval for transmitting the data in thecombinational logic unit 104 is the transmitting time interval 116.Moreover, the set-up time interval 118 is related to the state settingof the flip-flop 106. Therefore, the delay (critical timing) 112 can beconsidered to be the sum of the CK-Q time interval 114, the transmittingtime interval 116, and the set-up time interval 118.

In conventional structures using multiplexers in addition to the latcheseither for multiple inputs or multiple latches, the multiplexer delayworsens the CK-Q time 114 or the set-up time 118, depending on where themultiplexer is placed. As a result, they have longer delay time 112.Also, even if a conventional structure does not use a multiplexer,reducing the delay time 112 is still an important issue. Accordingly,new structures and methods for flip-flops are desired that can reducethe overall delay 112.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1A is an example circuit block diagram of a typical delay path in adigital circuit;

FIG. 1B is an example clock diagram of the operating delay of FIG. 1A;

FIG. 2 illustrates a high-level block diagram for a flip-flop structureaccording to one aspect of this disclosure;

FIG. 3 illustrates an exemplary embodiment of a flip-flop structureshown in FIG. 2; and

FIG. 4 illustrates an alternative embodiment of the scan enable (SE)signal for a flip-flop structure shown in FIG. 3.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent disclosure provides many applicable concepts that can beembodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the embodiments disclosed, and do not limit the scope of theinvention.

A flip-flop structure with reduced set-up time is provided. Throughoutthe various views and illustrative embodiments of the presentdisclosure, like reference numbers are used to designate like elements.

FIG. 2 illustrates a high-level block diagram for a flip-flop structureaccording to one aspect of this disclosure. The flip-flop 200 withreduced set-up time comprises the first master latch 202, the secondmaster latch 204, and a slave latch 206. The function data input D isconnected to the first master latch 202 and the scan data input (SI) isconnected to the second master latch 204. The second master latch 204 iscoupled to the first master latch 202 and the first master latch 202 isconnected to the slave latch 206. The scan data in general has a clockrate less than 50 MHz and preset patterns, e.g. texting, etc. Also, thescan data can be predefined with specific logic. The function datatypically has a clock rate faster than the scan data.

The present disclosure discloses embodiments that use two differentmaster latches to separately process the function data and the scandata, such that it is not required for the flip-flop to achieve theunification of the clock for the process of the function data and thescan data. The second master latch 204 receiving the scan data input(SI) latches the scan data to the slave latch 206 when a control signalfor the scan data is enabled. Otherwise, the first master latch 202receiving the function data latches the function data to the slave latch206. Because the second master latch 204 is coupled to the first masterlatch 202 without using a multiplexer, this structure reduces the set-uptime of the flip-flop. Also, because the function data and the scan dataare separately input to the first master latch 202 and the second masterlatch 204, there is no need to use a multiplexer for multiple inputs toa single latch. Using a multiplexer for multiple inputs will requirelonger set up time.

FIG. 3 illustrates an exemplary embodiment of a flip-flop structureshown in FIG. 2. The flip-flop 300 includes a first master latch 202, asecond master latch 204, a slave latch 206, switches 302, 304, 306, 308,310, 312, 314, 316, and inverters 320, 322, 324, 326, 328, 330, 332,334, 336, 340, 342, 344, 346, 348, 350. The function data D is input tothe first master latch 202 through the inverter 320 and the switch 302.The first master latch 202 comprises switches 312, 314, and inverters344, 346. The switch 312 and 314 along with inverters 344 and 346control the master latch 202 output. The master latch 202 passes eitherthe function data D or the scan data SI to the slave latch 206 dependingon the scan enable (SE) and the clock (CK) signal.

The clock signal CK generates a clock signal CKB through the inverter324, and generates a clock signal CKD through the inverter 326. Theclock signal CKB and the clock signal CKD are used to control the ON/OFFof the switches 302, 304, 308, 310, 312, and 316. The SE signalgenerates a SE signal SEB through the inverter 328, and generates a SEsignal SED through the inverter 330. The SE signal SEB and the SE signalSED are used to control the ON/OFF of the switches 306 and 314. In thisembodiment, the SE signal does not change its state at the CK signal'shigh phase. The scan data is input to the second master latch 204through the inverter 322 and switch 304. The second master latch 204comprises the switch 310 and inverters 340 and 342, and is used to latchand output the scan data input (SI) to the first master latch 202.

Depending on the SE, either the function data D or the scan data SI islatched from the first master latch 202 to the slave latch 206 throughthe switch 308. The slave latch 206 comprises a switch 316 and inverters348 and 350. The slave latch 206 output is connected through inverters334 and 336 to the output signal Q and the inverted output signal QB.

FIG. 4 illustrates an alternative embodiment of the scan enable (SE)signal for a flip-flop structure shown in FIG. 3. The SE signal SEB isgenerated from a SE signal through the circuit including inverters 406,408, 410, 412, and switches 402, 404. The switches 402 and 404 arecontrolled by the clock signals CKB and CKD. The SE signal SED isgenerated from SEB through the inverter 414. Compared to the circuitshown in FIG. 3 where the SE signal does not change its state at the CKsignal's high phase, the SE signal in FIG. 4 will change its state atthe CK signal's high phase. The user's test methodology can decidewhether to use the scheme shown in FIG. 4 or not. The scheme in FIG. 4doesn't need to be used if the user could make sure that SE does notchange at clock's high phase. In this way, the size of this architectureis more compact. Otherwise, the scheme in FIG. 4 can be used toguarantee a correct function if SE will change its state at clock's highphase.

Although the present embodiments and their advantages have beendescribed in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, and composition of matter, means, methods and stepsdescribed in the specification. As one of ordinary skill in the art willreadily appreciate from the disclosure, processes, machines,manufacture, compositions of matter, means, methods, or steps, presentlyexisting or later to be developed, that perform substantially the samefunction or achieve substantially the same result as the correspondingembodiments described herein may be utilized according to the presentdisclosure.

1. A flip-flop, comprising: a first master latch receiving a functiondata; a second master latch receiving a scan data; and a slave latchconnected to the first master latch; wherein the second master latch iscoupled to the first master latch, the coupling between the secondmaster and the first master latch adapted to control whether thefunction data or the scan data becomes an output from the first masterlatch to the slave latch based on a scan enable signal, and the slavelatch is adapted to latch and transmit the output from the first masterlatch.
 2. The flip-flop of claim 1, wherein the first master latch isadapted to receive the function data through a switch controlled by aclock signal.
 3. The flip-flop of claim 1, wherein the second masterlatch is adapted to receive the scan data through a switch controlled bya clock signal.
 4. The flip-flop of claim 1, wherein the first masterlatch is connected to the slave latch through a switch controlled by aclock signal.
 5. The flip-flop of claim 1, wherein the second masterlatch is coupled to the first master latch through a switch controlledby the scan enable signal.
 6. The flip-flop of claim 1, wherein thefirst master latch comprises a first switch, a second switch, a firstinverter, a second inverter, and the first switch is controlled by aclock signal, the second switch is controlled by the scan enable signal,the first inverter is coupled to the second inverter through the secondswitch, and the flip-flop is adapted to pass the function data or thescan data to the slave latch depending on the scan enable signal.
 7. Theflip-flop of claim 6, wherein the second master latch comprises a thirdswitch, a third inverter, a fourth inverter, and the third switch iscontrolled by the clock signal, the third inverter is coupled to thefourth inverter through the third switch, so as to latch and output thescan data.
 8. The flip-flop of claim 7, wherein the second master latchis coupled to the first master latch in between the first switch and thesecond switch.
 9. The flip-flop of claim 1, wherein the slave latchcomprises a first switch, a first inverter, a second inverter, and thefirst switch is controlled by a clock signal, the first inverter iscoupled to the second inverter through the first switch, so as to latchand transmit the output from the first master latch.
 10. The flip-flopof claim 1, wherein the scan enable signal does not change at a highphase of a clock signal.
 11. The flip-flop of claim 1, wherein the scanenable signal changes at a high phase of a clock signal.
 12. Aflip-flop, comprising: a first master latch adapted to receive afunction data through a first switch, the first switch adapted to becontrolled by a clock signal; a second master latch adapted to receive ascan data through a second switch, the second switch adapted to becontrolled by the clock signal; and a slave latch connected to the firstmaster latch through a third switch, the third switch adapted to becontrolled by the clock signal; wherein the second master latch iscoupled to the first master latch through a fourth switch adapted to becontrolled by a scan enable signal so that the flip-flop is adapted tocontrol whether the function data or the scan data becomes an outputfrom the first master latch to the slave latch based on the scan enablesignal, and the slave latch is adapted to latch and transmit the outputfrom the first master latch.
 13. The flip-flop of claim 12, wherein thefirst master latch comprises a fifth switch, a sixth switch, a firstinverter, a second inverter, and the fifth switch is controlled by theclock signal, the sixth switch is controlled by the scan enable signal,the first inverter is coupled to the second inverter through the sixthswitch, and the flip-flop is adapted to pass the function data or thescan data to the slave latch depending on the scan enable signal. 14.The flip-flop of claim 13, wherein the second master latch comprises aseventh switch, a third inverter, a fourth inverter, and the seventhswitch is controlled by the clock signal, the third inverter is coupledto the fourth inverter through the seventh switch, so as to latch andoutput the scan data.
 15. The flip-flop of claim 14, wherein the secondmaster latch is coupled to the first master latch in between the fifthswitch and the sixth switch.
 16. The flip-flop of claim 15, wherein theslave latch comprises an eighth switch, a fifth inverter, a sixthinverter, and the eighth switch is controlled by the clock signal, thefifth inverter is coupled to the sixth inverter through the eighthswitch, so as to latch and transmit the output from the first masterlatch.
 17. The flip-flop of claim 12, wherein the scan enable signaldoes not change at a high phase of the clock signal.
 18. The flip-flopof claim 12, wherein the scan enable signal changes at a high phase ofthe clock signal.
 19. A flip-flop, comprising: a first master latchadapted to receive a function data through a first switch, the firstswitch adapted to be controlled by a clock signal; a second master latchadapted to receiving a scan data through a second switch, the secondswitch adapted to be controlled by the clock signal; and a slave latchconnected to the first master latch through a third switch, the thirdswitch adapted to be controlled by the clock signal; wherein the secondmaster latch is coupled to the first master latch through a fourthswitch adapted to be controlled by a scan enable signal so that theflip-flop is adapted to control whether the function data or the scandata becomes an output from the first master latch to the slave latchbased on the scan enable signal, the slave latch is adapted to latch andtransmit the output from the first master latch, and the scan enablesignal adapted to change at a high phase of the clock signal.
 20. Theflip-flop of claim 19, wherein the first master latch comprises a fifthswitch, a sixth switch, a first inverter, a second inverter, and thefifth switch is controlled by the clock signal, the sixth switch isadapted to be controlled by the scan enable signal, the first inverteris coupled to the second inverter through the sixth switch, theflip-flop adapted to pass the function data or the scan data to theslave latch depending on the scan enable signal, and the second masterlatch is coupled to the first master latch in between the fifth switchand the sixth switch.